This invention relates to electrical interconnection of integrated circuit chips and, particularly, to mounting interconnected stacked die onto a support.
A typical semiconductor die has a front (“active”) side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges. Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed. Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows at the front side near the center of the die, and these may be referred to as center pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die.
Semiconductor die may be electrically connected with other circuitry in a package, for example on a package substrate or on a leadframe, by any of several means. Such z-interconnection may be made, for example, by wire bonds, or by flip chip interconnects, or by tab interconnects. The package substrate or leadframe provides for electrical connection of the package to underlying circuitry (second-level interconnection), such as circuitry on a printed circuit board, in a device in which the package is installed for use.
A number of approaches have been proposed for increasing the density of active semiconductor circuitry in integrated circuit chip packages, while minimizing package size (package footprint, package thickness). In one approach to making a high density package having a smaller footprint, two or more semiconductor die, of the same or different functionality, are stacked one over another and mounted on a package substrate.
The disclosure of U.S. Pat. No. 7,245,021 describes a vertically stacked die assembly including a plurality of integrated circuit die electrically interconnected by “vertical conducting elements”. The die are covered with an electrically insulative conformal coating. The vertical conducting elements are formed of a conductive polymer material, applied adjacent the edge of the die. The die are provided with metallic conducting elements, each having one end attached to electrical connection points at the die periphery and having the other end embedded in a vertical conducting polymer element. The disclosure of U.S. Pat. No. 7,215,018 describes a similar vertically stacked die assembly mounted onto a ball grid array (“BGA”) or land grid array (“LGA”) substrate. The stacked die assembly is mounted onto the BGA or LGA substrate by electrical and physical connection of the vertical conducting elements (“vertical interconnects”) to electrical connection lands on the surface of the substrate. The electrical connection is said to be done by use of a conductive polymer “dot” or “puddle” between the vertical interconnect of the stack of die and the substrate. The patent discloses that the substrate can include means for making electrical connection between the bottom of the substrate and a printed circuit board, such as solder balls or bumps, or “LGA contacts” on the bottom of the substrate.